View LTC3416EFETR_6236290.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ltc3416 1 3416fa , ltc and lt are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. opti-loop is a registered trade- mark of linear technology corporation. protected by u.s. patents including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131, 6724174. high efficiency: up to 95% 4a output current low r ds(on) internal switch: 67m ? tracking input to provide easy supply sequencing programmable frequency: 300khz to 4mhz 2.25v to 5.5v input voltage range 2% output voltage accuracy 0.8v reference allows low output voltage low dropout operation: 100% duty cycle power good output voltage monitor overtemperature protected available in a 20-lead thermally enhanced tssop package 4a, 4mhz, monolithic synchronous step-down regulator with tracking portable instruments notebook computers distributed power systems battery-powered equipment pol board power svin pgood 22 f v out2 2.5v 100 f 2 v out1 1.8v 4a 0.2 h sw ltc3416 pgnd sgnd r t run/ss i th track pvin v fb 127k 7.5k 200k 255k 200k 255k 3416 f01a 820pf v in 2.5v to 5.5v i/o voltage figure 1a. 2.5v/4a step-down regulator with tracking the ltc ? 3416 is a high efficiency monolithic synchro- nous, step-down dc/dc converter utilizing a constant frequency, current mode architecture. it operates from an input voltage range of 2.25v to 5.5v and provides a regulated output voltage from 0.8v to 5v while delivering up to 4a of output current. the internal synchronous power switch with 67m ? of on-resistance increases effi- ciency and eliminates the need for an external schottky diode. switching frequency is set by an external resistor. 100% duty cycle provides low dropout operation extend- ing battery life in portable systems. opti-loop ? compen- sation allows the transient response to be optimized over a wide range of loads and output capacitors. the ltc3416 operates in forced continuous operation and provides tracking of another power supply rail. forced continuous operation reduces noise and rf interference and provides excellent transient response. fault protection is provided by an overcurrent comparator, and adjustable compensation allows the transient response to be optimized over a wide range of loads and output capacitors. figure 1b. efficiency vs load current load current (a) 0.01 40 efficiency (%) 50 60 70 80 0.10 1 10 3416 g09 30 20 10 0 90 100 v in = 2.5v v out = 1.8v f = 2mhz v in = 3.3v features descriptio u applicatio s u typical applicatio u
ltc3416 2 3416fa symbol parameter conditions min typ max units v in input voltage range 2.25 5.5 v v fb regulated feedback voltage (note 3) 0.784 0.800 0.816 v i fb feedback input current 0.2 a i track track input current 0.2 a ? v fb reference voltage line regulation v in = 2.5v to 5.5v (note 3) 0.04 0.2 %/v v track tracking voltage offset v track = 0.4v 30 mv tracking voltage range 0 0.8 v v loadreg output voltage load regulation measured in servo loop, v ith = 0.36v 0.02 0.2 % measured in servo loop, v ith = 0.84v C0.02 C0.2 % ? v pgood power good range 7.5 9% r pgood power good resistance 120 200 ? i q input dc bias current (note 4) active current v fb = 0.7v, v ith = 1.2v 300 350 a shutdown v run = 0v 0.02 1 a f osc switching frequency r osc = 294k ? 0.88 1 1.12 mhz switching frequency range (note 4) 0.30 4.00 mhz r pfet r ds(on) of p-channel fet i sw = 300ma 67 100 m ? r nfet r ds(on) of n-channel fet i sw = C300ma 50 100 m ? i limit peak current limit 68 a v uvlo undervoltage lockout threshold 1.75 2 2.25 v i lsw sw leakage current v run = 0v, v in = 5.5v 0.1 1 a v run run threshold 0.5 0.65 0.8 v input supply voltage .................................. C 0.3v to 6v i th , run, v fb voltages .............................. C 0.3v to v in track voltage .......................................... C 0.3v to v in sw voltage .................................. C 0.3v to (v in + 0.3v) operating ambient temperature range (note 2) .................................................. C 40 c to 85 c junction temperature (notes 5, 6) ...................... 125 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c order part number (note 1) absolute axi u rati gs w ww u package/order i for atio uu w consult ltc marketing for parts specified with wider operating temperature ranges. ltc3416efe t jmax = 125 c, ja = 38 c/w, jc = 10 c/w exposed pad is gnd (pin 21) must be soldered to pcb the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 3.3v, unless otherwise noted. electrical characteristics fe package 20-lead plastic tssop 1 2 3 4 5 6 7 8 9 10 top view 20 19 18 17 16 15 14 13 12 11 pgnd r t track run/ss sgnd nc pv in sw sw pgnd pgnd v fb i th pgood sv in nc pv in sw sw pgnd 21 order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/
ltc3416 3 3416fa note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. the voltage should never exceed 6.0v for any pin. note 2: the ltc3416e is guaranteed to meet performance specifications from 0 c to 85 c. specifications over the C40 c to 85 c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 3: the ltc3416 is tested in a feedback loop that adjusts v fb to achieve a specified error amplifier output voltage (i th ). note 4: this parameter is guaranteed by design and characterization. electrical characteristics typical perfor a ce characteristics uw switch on-resistance vs input voltage temperature ( c) C40 0.795 v ref (v) 0.796 0.798 0.799 0.800 0 40 60 140 3416 g01 0.797 C20 20 80 100 120 input voltage (v) 2.25 2.75 3.25 3.75 4.25 4.75 5.25 5.75 on-resistance (m ? ) 90 80 70 60 50 40 30 20 10 0 3416 g02 pfet nfet t a = 25 c temperature ( c) C40 on-resistance (m ? ) 120 100 80 60 40 20 0 C25 3416 g03 C10 520 35 50 65 80 95 110 125 pfet nfet v ref vs temperature, v in = 3.3v switch on-resistance vs temperature, v in = 3.3v switch leakage vs input voltage input voltage (v) 2.25 switch leakage current (na) 20 18 16 14 12 10 8 6 4 2 0 3.25 4.25 4.75 3416 g04 2.75 3.75 5.25 pfet nfet t a = 25 c frequency vs r osc r osc (k) 25 frequency (khz) 7000 6000 5000 4000 3000 2000 1000 0 3416 g05 225 925 825 725 625 525 125 325 425 v in = 3.3v t a = 25 c frequency vs input voltage input voltage (v) 2.25 3.25 4.25 4.75 2.75 3.75 5.25 1040 1020 1000 980 960 940 920 900 3416 g06 frequency (khz) r osc = 294k t a = 25 c note 5: dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. note 6: t j is calculated from the ambient temperature t a and power dissipation p d as follows: ltc3416e: t j = t a + (p d )(38 c/w) note 7: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125 c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability.
ltc3416 4 3416fa typical perfor a ce characteristics uw dc supply current vs input voltage frequency vs temperature efficiency vs load current, forced continuous temperature ( c) C40 60 1090 1070 1050 1030 1010 990 970 950 930 910 3416 g07 C20 120 02040 80 100 frequency (khz) v in = 3.3v r osc = 294k input voltage (v) 2.25 400 350 300 250 200 150 100 50 0 3.75 4.75 3416 g08 2.75 3.25 4.25 5.25 quiescent current ( a) load step transient efficiency vs input voltage input voltage (v) 2.5 efficiency (%) 3.0 3.5 4.0 4.5 3416 g10 5.0 98 96 94 92 90 88 86 84 82 80 78 5.5 i out = 1a i out = 4a v out = 2.5v t a = 25 c load regulation load current (a) ? v out /v out (%) 3416 g11 0 C0.20 C0.40 C0.60 C0.80 C1.00 C1.20 C1.40 0 1.0 2.0 2.5 0.5 1.5 3.0 3.5 4.0 v in = 3.3v v out = 1.8v 3416 g12 v in = 3.3v, v out = 1.8v f = 2mhz load step = 0a to 4a v out inductor current 2a/div 20 s/div 3416 g13 v in = 3.3v, v out = 1.8v tracking 2.5v 5ms/div tracking: start-up and shutdown load current (a) 0.01 40 efficiency (%) 50 60 70 80 0.10 1 10 3416 g09 30 20 10 0 90 100 v in = 2.5v v in = 3.3v v out = 1.8v f = 2mhz
ltc3416 5 3416fa uu u pi fu ctio s pgnd (pins 1, 10, 11, 20): power ground. connect this pin closely to the (C) terminal of c in and c out . r t (pin 2): oscillator resistor input. connecting a resistor to ground from this pin sets the switching frequency. track (pin 3): tracking voltage input. applying a voltage that is less than 0.8v to this pin enables tracking. during tracking, the v fb pin will regulate to the voltage on this pin. do not float this pin. run/ss (pin 4): run control and soft-start input. forcing this pin below 0.5v shuts down the ltc3416. in shutdown all functions are disabled, drawing <1 a of supply current. a capacitor to ground from this pin sets the ramp time to full output current. sgnd (pin 5): signal ground. all small-signal compo- nents and compensation components should connect to this ground, which in turn connects to pgnd at one point. nc (pins 6, 15): no connect. pv in (pins 7, 14): power input supply. decouple this pin to pgnd with a capacitor. sw (pins 8, 9, 12, 13): switch node connection to inductor. this pin connects to the drains of the internal main and synchronous power mosfet switches. sv in (pin 16): signal input supply. decouple this pin to the sgnd capacitor. pgood (pin 17): power good output. open-drain logic output that is pulled to ground when the output voltage is not within 7.5% of the regulation point. i th (pin 18): error amplifier compensation point. the current comparator threshold increases with this control voltage. nominal voltage range for this pin is from 0.2v to 1.4v with 0.4v corresponding to the zero-sense voltage (zero current). v fb (pin 19): feedback pin. receives the feedback voltage from a resistive divider connected across the output. exposed pad (pin 21): ground. connect to sgnd.
ltc3416 6 3416fa fu ctio al diagra u u w C + C + C + C + 19 error amplifier 0.74v v fb 3 track sv in 4 run/ss 17 pgood run 0.86v C + voltage reference slope compensation oscillator r t logic slope compensation recovery pmos current comparator nmos current comparator 16 sgnd 5 exposed pad 21 i th 18 sw pgnd 3416 fd 8 pv in 7 14 9 12 13 1 10 11 20 2 operatio u main control loop the ltc3416 is a monolithic, constant frequency, current mode step-down dc/dc converter. during normal opera- tion, the internal top power switch (p-channel mosfet) is turned on at the beginning of each clock cycle. current in the inductor increases until the current comparator trips and turns off the top power mosfet. the peak inductor current at which the current comparator shuts off the top power switch is controlled by the voltage on the i th pin. the error amplifier adjusts the voltage on the i th pin by comparing the feedback signal from a resistor divider on the v fb pin with an internal 0.8v reference. when the load current increases, it causes a reduction in the feedback voltage relative to the reference. the error amplifier raises the i th voltage until the average inductor current matches the new load current. when the top power mosfet shuts off, the synchronous power switch (n-channel mosfet) turns on until either the bottom current limit is reached or the beginning of the next clock cycle. the bottom current limit is set at C5a. the operating frequency is externally set by an external resistor connected between the r t pin and ground. the practical switching frequency can range from 300khz to 4mhz. overvoltage and undervoltage comparators will pull the pgood output low if the output voltage comes out of regulation by 7.5%. in an overvoltage condition, the top
ltc3416 7 3416fa operatio u power mosfet is turned off and the bottom power mos- fet is switched on until either the overvoltage condition clears or the bottom mosfets current limit is reached. voltage tracking some microprocessors, asic and dsp chips need two power supplies with different voltage levels. these sys- tems often require voltage sequencing between the core power supply and the i/o power supply. without proper sequencing, latch-up failure or excessive current draw may occur that could result in damage to the processors i/o ports or the i/o ports of supporting system devices such as memory, fpgas or data converters. to ensure that the i/o loads are not driven until the core voltage is properly biased, tracking of the core supply voltage and the i/o supply voltage is necessary. voltage tracking is enabled by applying a voltage to the track pin. when the voltage on the track pin is below 0.8v, the feedback voltage will regulate to this tracking voltage. when the tracking voltage exceeds 0.8v, tracking control over the feedback voltage is gradually released. full release of tracking control over the feedback voltage is achieved when the tracking voltage exceeds 1.05v. dropout operation when the input supply voltage decreases toward the output voltage, the duty cycle increases toward the maxi- mum on-time. further reduction of the supply voltage forces the main switch to remain on for more than one cycle, eventually reaching 100% duty cycle. the output voltage will then be determined by the input voltage minus the voltage drop across the internal p-channel mosfet and the inductor. low supply operation the ltc3416 is designed to operate down to an input supply voltage of 2.25v. one important consideration at low input supply voltages is that the r ds(on) of the p-channel and n-channel power switches increases. the user should calculate the power dissipation when the ltc3416 is used at 100% duty cycle with low input voltages to ensure that thermal limits are not exceeded. slope compensation and inductor peak current slope compensation provides stability in constant fre- quency architectures by preventing subharmonic oscilla- tions at duty cycles greater than 50%. it is accomplished internally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. normally, the maximum inductor peak current is reduced when slope compensation is added. in the ltc3416, however, slope compensation recovery is implemented to keep the maximum inductor peak current constant throughout the range of duty cycles. this keeps the maximum output current relatively constant regardless of duty cycle. short-circuit protection when the output is shorted to ground, the inductor current decays very slowly during a single switching cycle. to prevent current runaway from occurring, a secondary current limit is imposed on the inductor current. if the inductor valley current exceeds 7.8a, the top power mos- fet will be held off and switching cycles will be skipped until the inductor current is reduced.
ltc3416 8 3416fa applicatio s i for atio wu uu the basic ltc3416 application circuit is shown in figure 1a. external component selection is determined by the maxi- mum load current and begins with the selection of the operating frequency and inductor value followed by c in and c out . operating frequency selection of the operating frequency is a tradeoff between efficiency and component size. high frequency operation allows the use of smaller inductor and capacitor values. operation at lower frequencies improves efficiency by reducing internal gate charge losses but requires larger inductance values and/or capacitance to maintain low output ripple voltage. the operating frequency of the ltc3416 is determined by an external resistor that is connected between the r t pin and ground. the value of the resistor sets the ramp current that is used to charge and discharge an internal timing capacitor within the oscillator and can be calculated by using the following equation: r f k osc = ? () ? 308 10 10 11 .? C although frequencies as high as 4mhz are possible, the minimum on-time of the ltc3416 imposes a minimum limit on the operating duty cycle. the minimum on-time is typically 110ns. therefore, the minimum duty cycle is equal to 100 ? 110ns ? f(hz). inductor selection for a given input and output voltage, the inductor value and operating frequency determine the ripple current. the ripple current ? i l increases with higher v in or lower v out and decreases with higher inductance. ? = ? ? ? ? ? ? ? ? ? ? ? ? i v fl v v l out out in 1C having a lower ripple current reduces the core losses in the inductor, the esr losses in the output capacitors and the output voltage ripple. highest efficiency operation is achieved at low frequency with small ripple current. this, however, requires a large inductor. a reasonable starting point for selecting the ripple current is ? i l = 0.4(i max ). the largest ripple current occurs at the highest v in . to guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation: l v fi v v out l max out in max = ? ? ? ? ? ? ? ? ? ? ? ? ? () () C 1 inductor core selection once the value for l is known, the type of inductor must be selected. actual core loss is independent of core size for a fixed inductor value, but it is very dependent on the inductance selected. as the inductance increases, core losses decrease. unfortunately, increased inductance re- quires more turns of wire and therefore copper losses will increase. ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can con- centrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that induc- tance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! different core materials and shapes will change the size/ current and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy mate- rials are small and dont radiate much energy, but gener- ally cost more than powdered iron core inductors with similar characteristics. the choice of which style inductor to use mainly depends on the price vs size requirements and any radiated field/emi requirements. new designs for surface mount inductors are available from coiltronics, coilcraft, toko and sumida. c in and c out selection the input capacitance, c in , is needed to filter the trapezoi- dal wave current at the source of the top mosfet. to
ltc3416 9 3416fa applicatio s i for atio wu uu prevent large voltage transients from occurring, a low esr input capacitor sized for the maximum rms current should be used. the maximum rms current is given by: ii v v v v rms out max out in in out = () C1 this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher tempera- ture than required. several capacitors may also be paral- leled to meet size or height requirements in the design. for low input voltage applications, sufficient bulk input ca- pacitance is needed to minimize transient effects during output load changes. the selection of c out is determined by the effective series resistance (esr) that is required to minimize voltage ripple and load step transients as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response as described in a later section. the output ripple, ? v out , is determined by: ?? + ? ? ? ? ? ? v i esr fc out l out 1 8 the output ripple is highest at maximum input voltage since ? i l increases with input voltage. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special poly- mer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. special polymer capacitors offer very low esr but have lower capacitance density than other types. tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. aluminum electrolytic capacitors have significantly higher esr, but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. ceramic capaci- tors have excellent low esr characteristics but can have a high voltage coefficient and audible piezoelectric effects. the high q of ceramic capacitors with trace inductance can also lead to significant ringing. using ceramic input and output capacitors higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, care must be taken when these capacitors are used at the input and output. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, v in . at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. when choosing the input and output ceramic capacitors, choose the x5r or x7r dielectric formulations. these dielectrics have the best temperature and voltage charac- teristics of all the ceramics for a given value and size. output voltage programming the output voltage is set by an external resistive divider according to the following equation: vv r r out =+ ? ? ? ? ? ? 08 1 2 1 . the resistive divider allows the v fb pin to sense a fraction of the output voltage as shown in figure 2. figure 2. setting the output voltage ltc3416 sgnd r1 3416 f02 r2 v fb v out voltage tracking the ltc3416 allows the user to program how its output voltage ramps during start-up by means of the track pin. through this pin, the output voltage can be set up to either
ltc3416 10 3416fa applicatio s i for atio wu uu coincidentally or ratiometrically track another output volt- age as shown in figure 3. if the voltage on the track pin is less than 0.8v, voltage tracking is enabled. during voltage tracking, the output voltage regulates to the tracking voltage through a resistor divider network. the output voltage during tracking can be calculated with the following equation: vv r r out track =+ ? ? ? ? ? ? 1 2 1 , v track < 0.8v voltage tracking can be accomplished by sensing a frac- tion of the output voltage from another regulator. this is typically done by using a resistor divider to attenuate the output voltage that is being tracked. setting this attenua- tion factor equal to the reciprocal of the gain factor provided by the feedback resistors will force the regulator outputs to be equal to each other during tracking. if tracking is not desired, connect the track pin to sv in . to implement the coincident tracking shown in figure 3a, connect an extra resistor divider to the output of v out2 and connect its midpoint to the track pin of the ltc3416 as shown in figure 4. the ratio of this divider should be selected the same as that of v out1 s resistor divider. to implement the ratiometric sequencing in figure 3b, the extra resistor dividers ratio should be set so that the track pin voltage exceeds 1.05v by the end of the start- up period. the ltc3416 utilizes a method in which the track pins control over the output voltage is gradually released as the track pin voltage approaches 0.8v. with this technique, some overdrive will be required on the track pin to ensure that the tracking function is com- pletely disabled at the end of the start-up period. for coincident tracking, the following condition should be satisfied to ensure that tracking is disabled at the end of start-up. v out2 1.32 v out1 for ratiometric tracking, the following equation can be used to calculate the resistor values: rr v v vv out track track 43 1 105 2 = ? ? ? ? ? ? C . time (3a) coincident tracking v out2 v out1 output voltage time 3416 f03 (3b) ratiometric sequencing v out2 v out1 output voltage figure 3. two different modes of output voltage sequencing figure 4. setup for tracking and ratiometric sequencing r4 r2 r3 r1 to v fb(master) pin to track pin v out2 3416 f04
ltc3416 11 3416fa applicatio s i for atio wu uu an alternative method of tracking is shown in figure 5. for the circuit of figure 5, the following equations can be used to determine the resistor values: vv r r vv rr r rr v v out out out out 1 2 2 1 08 1 2 1 08 1 45 3 43 1 =+ ? ? ? ? ? ? =+ + ? ? ? ? ? ? = ? ? ? ? ? ? . . C soft-start the run/ss pin provides a means to shut down the ltc3416 as well as a timer for soft-start. pulling the run/ ss pin below 0.5v places the ltc3416 in a low quiescent current shutdown state (i q < 1 a). the soft-start gradually raises the clamp on i th . the full current range becomes available on i th after the voltage on i th reaches approximately 2v. the clamp on i th is set externally with a resistor and capacitor on the run/ss pin. the soft-start duration can be calculated by using the following formula: trcin v vv seconds ss ss ss in in = ? ? ? ? ? ? C. () 18 efficiency considerations the efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. efficiency can be expressed as: efficiency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percentage of input power. although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses: v in quiescent current and i 2 r losses. the v in quiescent current loss dominates the efficiency loss at very low load currents whereas the i 2 r loss dominates the efficiency loss at medium to high load currents. in a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence. 1. the v in quiescent current is due to two components: the dc bias current as given in the electrical characteristics and the internal main switch and synchronous switch gate charge currents. the gate charge current results from switching the gate capacitance of the internal power mosfet switches. each time the gate is switched from high to low to high again, a packet of charge dq moves from v in to ground. the resulting dq/dt is the current out of v in that is typically larger than the dc bias current. in continuous mode, i gatechg = f(q t + q b ) where q t and q b are the gate charges of the internal top and bottom switches. both the dc bias and gate charge losses are proportional to v in and thus their effects will be more pronounced at higher supply voltages. 2. i 2 r losses are calculated from the resistances of the internal switches, r sw , and external inductor r l . in continuous mode the average output current flowing through inductor l is chopped between the main switch and the synchronous switch. thus, the series resistance looking into the sw pin is a function of both top and bottom mosfet r ds(on) and the duty cycle (dc) as follows: r sw = (r ds(on)top )(dc) + (r ds(on)bot )(1 C dc) figure 5. dual voltage system with tracking ltc3416 sgnd r1 3416 f05 r2 v fb track v out1 ltc3416 slave master sgnd r3 r4 r5 v fb v out2
ltc3416 12 3416fa applicatio s i for atio wu uu the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance characteris- tics curves. thus, to obtain i 2 r losses, simply add r sw to r l and multiply the result by the square of the average output current. other losses including c in and c out esr dissipative losses and inductor core losses generally account for less than 2% of the total loss. in most applications, the ltc3416 does not dissipate much heat due to its high efficiency. but in applications where the ltc3416 is running at high ambient tempera- ture with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. if the junction tempera- ture reaches approximately 150 c, both power switches will be turned off and the sw node will become high impedance. to avoid the ltc3416 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. the goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. the tempera- ture rise is given by: t r = (p d )( ja ) where p d is the power dissipated by the regulator and ja is the thermal resistance from the junction of the die to the ambient temperature. for the 20-lead exposed tssop package, the ja is 38 c/w. the junction temperature, t j , is given by: t j = t a + t r where t a is the ambient temperature. note that at higher supply voltages, the junction tempera- ture is lower due to reduced switch resistance (r ds(on) ). to maximize the thermal performance of the ltc3416, the exposed pad should be soldered to a ground plane. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to ? i load (esr), where esr is the effective series resistance of c out . ? i load also begins to charge or discharge c out generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability prob- lem. the i th pin external components and output capaci- tor shown in figure 1a will provide adequate compensation for most applications. design example as a design example, consider using the ltc3416 in an application with the following specifications: v in = 3.3v, v out1 = 1.8v, v out2 = 2.5v, i out1(max) = i out2(max) = 4a, f = 1mhz. v out1 and v out2 must track when powering up and powering down. first, calculate the timing resistor: rkk osc == 308 10 110 10 298 11 6 .? ? C use a standard value of 294k ? . next, calculate the induc- tor values for about 40% ripple current: l v mhz a v v h l v mhz a v v h 1 18 116 1 18 33 051 2 25 116 1 25 33 038 = ? ? ? ? ? ? ? ? ? ? ? ? = = ? ? ? ? ? ? ? ? ? ? ? ? = . ?. C . . . . ?. C . . . using a 0.47 h inductor for both results in maximum ripple currents of: ? = ? ? ? ? ? ? ? ? ? ? ? ? = ? = ? ? ? ? ? ? ? ? ? ? ? ? = i v mhz h v v a i v mhz h v v a l l 1 2 18 1047 1 18 33 174 25 1047 1 25 33 129 . ?. C . . . . ?. C . . . c out1 and c out2 will be selected based on the esr that is required to satisfy the output voltage ripple requirement and the bulk capacitance needed for loop stability. for this design, two 100 f ceramic capacitors will be used at each output.
ltc3416 13 3416fa applicatio s i for atio wu uu c in1 and c in2 should be sized for a maximum current rating of: ia v v v v a ia v v v v a rms rms rms rms 1 2 4 18 33 33 18 1199 4 25 33 33 25 1171 = ? ? ? ? ? ? = = ? ? ? ? ? ? = . . . . C. . . . . C. decoupling the pv in and sv in pins with two 100 f capaci- tors on both switching regulators is adequate for most applications. the resitor values for the voltage divider on v out1 can be calculated by using the following equation: 18 08 1 2 1 .. vv r r =+ ? ? ? ? ? ? setting r1 to 200k results in a value of 255k for r2. to calculate the resistor values for the voltage divider on v out2 , we can use the following equations: rr v v vv rr r 43 25 18 1 25 08 1 45 3 = ? ? ? ? ? ? =+ + ? ? ? ? ? ? . . C .. setting r3 to 205k gives the following results: r4 = 78.7k and r5 = 357k. figure 6 shows the complete schematic for this design example. figure 6. 1.8v and 2.5v, 4a voltage tracking regulators at 1mhz l2* 0.47 h c ff2 22pf x7r r5 357k r4 78.7k ltc3416 pv in pv in sv in run pgood track r t sgnd pgnd pgnd sw sw sw sw v fb nc nc i th pgnd pgnd 7 14 16 4 17 3 2 5 1 10 8 9 12 13 19 6 15 18 20 11 c ith2 680pf x7r r3 205k r ith2 5.9k r pg2 100k r ss 2.2m c ss 1000pf r osc2 294k c in2 ** 100 f 2 v in 3.3v pgood c out2 ** 100 f 2 c c2 22pf x7r v out2 2.5v 4a l1* 0.47 h c ff1 22pf x7r r2 255k pv in pv in sv in run pgood track r t sgnd pgnd pgnd sw sw sw sw v fb nc nc i th pgnd pgnd 7 14 16 4 17 3 2 5 1 10 8 9 12 13 19 6 15 18 20 11 c ith1 680pf x7r r1 200k r ith1 5.9k r pg1 100k r osc1 294k toko fdvo630-r47m tdk c4532x5r0j107m * ** c in1 ** 100 f 2 v in 3.3v pgood c out1 ** 100 f 2 c c1 22pf x7r 3416 f06 v out1 1.8v 4a ltc3416
ltc3416 14 3416fa applicatio s i for atio wu uu figure 7. ltc3416 layout diagram (7a) top layer (7b) bottom layer pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc3416. check the following in your layout. 1. a ground plane is recommended. if a ground plane layer is not used, the signal and power grounds should be segregated with all small-signal components returning to the sgnd pin at one point which is then connected to the pgnd pin close to the ltc3416. 2. connect the (+) terminal of the input capacitor(s), c in , as close as possible to the pv in pin. this capacitor provides the ac current into the internal power mosfets. 3. keep the switching node, sw, away from all sensitive small-signal nodes. 4. flood all unused areas on all layers with copper. flood- ing with copper will reduce the temperature rise of power components. you can connect the copper areas to any dc net (pv in , sv in , v out , pgnd, sgnd or any other dc rail in your system). 5. connect the v fb pin directly to the feedback resistors. the resistor divider must be connected between v out and sgnd. 3416 f07a 3416 f07b
ltc3416 15 3416fa u package descriptio fe package 20-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663) exposed pad variation ca fe20 (ca) tssop 0204 0.09 C 0.20 (.0035 C .0079) 0 C 8 0.25 ref recommended solder pad layout 0.50 C 0.75 (.020 C .030) 4.30 C 4.50* (.169 C .177) 134 5 6 7 8910 11 12 14 13 6.40 C 6.60* (.252 C .260) 4.95 (.195) 2.74 (.108) 20 1918 17 16 15 1.20 (.047) max 0.05 C 0.15 (.002 C .006) 0.65 (.0256) bsc 0.195 C 0.30 (.0077 C .0118) typ 2 2.74 (.108) 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 4.95 (.195) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
ltc3416 16 3416fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2004 lt 1205 rev a ?printed in usa related parts part number description comments lt1616 500ma (i out ), 1.4mhz, high efficiency step-down 90% efficiency, v in : 3.6v to 25v, v out = 1.25v, dc/dc converter i q = 1.9ma, i sd < 1 a, thinsot package lt1676 450ma (i out ), 100khz, high efficiency step-down 90% efficiency, v in : 7.4v to 60v, v out = 1.24v, dc/dc converter i q = 3.2ma, i sd < 2.5 a, s8 package lt1765 25v, 2.75a (i out ), 1.25mhz, high efficiency step-down 90% efficiency, v in : 3v to 25v, v out = 1.2v, dc/dc converter i q = 1ma, i sd < 15 a, s8, tssop16e packages lt1776 500ma (i out ), 200khz, high efficiency step-down 90% efficiency, v in : 7.4v to 40v, v out = 1.24v, dc/dc converter i q = 3.2ma, i sd < 30 a, n8, s8 packages ltc1879 1.20a (i out ), 550khz, synchronous step-down 95% efficiency, v in : 2.7v to 10v, v out = 0.8v, dc/dc converter i q = 15 a, i sd < 1 a, tssop16 package ltc3405/ltc3405a 300ma (i out ), 1.5mhz, synchronous step-down 95% efficiency, v in : 2.75v to 6v, v out = 0.8v, dc/dc converter i q = 20 a, i sd < 1 a, thinsot package ltc3406/ltc3406b 600ma (i out ), 1.5mhz, synchronous step-down 95% efficiency, v in : 2.5v to 5.5v, v out = 0.6v, dc/dc converter i q = 20 a, i sd < 1 a, thinsot package ltc3411 1.25a (i out ), 4mhz, synchronous step-down 95% efficiency, v in : 2.5v to 5.5v, v out = 0.8v, dc/dc converter i q = 60 a, i sd < 1 a, ms, dfn packages ltc3412 2.5a (i out ), 4mhz, synchronous step-down 95% efficiency, v in : 2.5v to 5.5v, v out = 0.8v dc/dc converter i q = 60 a, i sd < 1 a, tssop16e package ltc3413 3a (i out sink/source), 2mhz, monolithic synchronous 90% efficiency, v in : 2.25v to 5.5v, v out = v ref /2, regulator for ddr/qdr memory termination i q = 280 a, i sd < 1 a, tssop16e package ltc3414 4a (i out ), 4mhz synchronous step-down regulator 95% efficiency, v in : 2.25v to 5v, v out to 0.8v, i q = 64 a, tssop28e package ltc3430 60v, 2.75a (i out ), 200khz, high efficiency step-down 90% efficiency, v in : 5.5v to 60v, v out = 1.2v, dc/dc converter i q = 2.5ma, i sd < 25 a, tssop16e package ltc3440 600ma (i out ), 2mhz, synchronous buck-boost 95% efficiency, v in : 2.5v to 5.5v, v out = 2.5v, dc/dc converter i q = 25 a, i sd < 1 a, ms package typical applicatio u l1* 0.68 h c2 22pf x7r r2 174k pv in pv in sv in run pgood track r t sgnd pgnd pgnd sw sw sw sw v fb nc nc i th pgnd pgnd 7 14 16 4 17 3 2 5 1 10 8 9 12 13 19 6 15 18 20 11 c ith 820pf x7r r1 200k r ith 7.5k r pg 100k r3 174k r4 200k r osc 294k vishay dale ihlp-2525cz-01 0.68 h tdk c4532x5r0j107m * ** c in1 ** 100 f v in 5v pgood c out ** 100 f 2 c1 47pf x7r 3416 ta01 v out1 1.5v 4a i/o supply 3.3v ltc3416 1.5v, 4a step-down regulator tracking from 3.3v i/o supply efficiency vs load current load current (a) 0.01 40 efficiency (%) 50 60 70 80 0.1 1 10 4316 ta02 30 20 10 0 90 100

▲Up To Search▲

Price & Availability of LTC3416EFETR

	To Download LTC3416EFETR Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .